View SST39VF100-70-4I-WI_670933.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. 1 mbit (64k x16) multi-purpose flash sst39lf100 / sst39vf100 features: ? organized as 64k x16 single voltage read and write operations ? 3.0-3.6v for sst39lf100 ? 2.7-3.6v for sst39vf100 superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption (typical values at 14 mhz) ? active current: 20 ma (typical) ? standby current: 3 a (typical) sector-erase capability ? uniform 2 kword sectors fast read access time ? 45 ns for sst39lf100 ? 70 ns for sst39vf100 latched address and data fast erase and word-program ? sector-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? word-program time: 14 s (typical) ? chip rewrite time: 1 second (typical) automatic write timing ? internal v pp generation end-of-write detection ? toggle bit ? data# polling cmos i/o compatibility jedec standard command sets packages available ? 40-lead tsop (10mm x 14mm) ? 48-ball tfbga (6mm x 8mm) product description the sst39lf/vf100 devices are 64k x16 cmos multi- purpose flash (mpf) manufactured with sst?s proprietary, high performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst39lf/vf100 write (pro- gram or erase) with a single voltage power supply of 3.0- 3.6v and 2.7-3.6v, respectively. featuring high performance word-program, the sst39lf/vf100 devices provide a typical word-program time of 14 sec. the devices use toggle bit or data# poll- ing to detect the completion of the program or erase oper- ation. to protect against inadvertent write, the sst39lf/ vf100 have on-chip hardware and software data protec- tion schemes. designed, manufactured, and tested for a wide spectrum of applications, the sst39lf/vf100 are offered with a guaranteed typical endurance of 10,000 cycles. data retention is rated at greater than 100 years. the sst39lf/vf100 devices are suited for applications that require convenient and economical updating of pro- gram, configuration, or data memory. for all system appli- cations, the sst39lf/vf100 significantly improve performance and reliability, while lowering power consump- tion. the sst39lf/vf100 inherently use less energy dur- ing erase and program than alternative flash technologies. the total energy consumed is a function of the applied volt- age, current, and time of application. since for any given voltage range, the superflash technology uses less cur- rent to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. the sst39lf/ vf100 also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet surface mount requirements, the sst39lf/vf100 are offered in 40-lead tsop and 48-ball tfbga packages. see figure 1 for pin assignments. device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. sst39lf/vf1003.0 & 2.7v 1mb (x16) mpf memories
2 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 read the read operation of the sst39lf/vf100 is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selec- tion. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 2). word-program operation the sst39lf/vf100 are programmed on a word-by-word basis. before programming, the sector where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the pro- gram operation, once initiated, will be completed within 20 s. see figures 3 and 4 for we# and ce# controlled pro- gram operation timing diagrams and figure 13 for flow- charts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal pro- gram operation, the host is free to perform additional tasks. any commands issued during the internal program opera- tion are ignored. sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sector architecture is based on uniform sector size of 2 kword. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the address lines a 11 -a 15 are used to determine the sector address. the sector address is latched on the falling edge of the sixth we# pulse, while the command (30h) is latched on the ris- ing edge of the sixth we# pulse. the internal erase opera- tion begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figure 8 for timing waveforms. any commands issued during the sector-erase operation are ignored. chip-erase operation the sst39lf/vf100 provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 7 for timing diagram, and figure 16 for the flowchart. any commands issued dur- ing the chip-erase operation are ignored. write operation status detection the sst39lf/vf100 provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which ini- tiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid.
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 3 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 data# polling (dq 7 ) when the sst39lf/vf100 are in the internal program operation, any attempt to read dq 7 will produce the com- plement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase opera- tion, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 5 for data# polling timing diagram and figure 14 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 6 for toggle bit tim- ing diagram and figure 14 for a flowchart. data protection the sst39lf/vf100 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst39lf/vf100 provide the jedec approved soft- ware data protection scheme for all data alteration opera- tions, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the sst39lf/vf100 devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid com- mands will abort the device to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. product identification the product identification mode identifies the devices as sst39lf/vf100 and manufacturer as sst. this mode may be accessed by software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manu- facturers in the same socket. for details, see table 4 for software operation, figure 9 for the software id entry and read timing diagram, and figure 15 for the software id entry command sequence flowchart. product identification mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to read mode. please note that the software id exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 10 for timing waveform, and figure 15 for a flowchart. table 1: p roduct i dentification address data manufacturer?s id 0000h 00bfh device id sst39lf/vf100 0001h 2788h t1.3 363
4 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 1: p in a ssignments for 40- lead tsop and 48- ball tfbga y-decoder i/o buffers and data latches 363 ill b1.2 address buffer & latches x-decoder dq 15 - dq 0 a 0 -a 15 oe# ce# we# superflash memory control logic f unctional b lock d iagram a13 a9 we# nc a7 a3 a12 a8 nc nc nc a4 a14 a10 nc nc a6 a2 a15 a11 nc nc a5 a1 nc dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 363 ill f02b.1 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h a9 a10 a11 a12 a13 a14 a15 nc we# v dd nc ce# dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v ss a8 a7 a6 a5 a4 a3 a2 a1 a0 oe# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 v ss 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 363 ill f01.3 standard pinout to p v i e w die up
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 5 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 table 2: p in d escription symbol pin name functions a 15 -a 0 address inputs to provide memory addresses. during sector-erase a 15 -a 11 address lines will select the sector. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 3.0-3.6v for sst39lf100 2.7-3.6v for sst39vf100 v ss ground nc no connection unconnected pins. t2.2 363 table 3: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih xxhigh z x write inhibit x v il xhigh z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.2 363 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 1. address format a 14 -a 0 (hex), addresses a 15 can be v il or v ih , but no other value, for the command sequence data 2 2. dq 15 - dq 8 can be v il or v ih , but no other value, for the command sequence addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 3. wa = program word address data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 4. sa x for sector-erase; uses a 15 -a 11 address lines 30h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5,6 5. the device does not remain in software product id mode if powered down. 6. with a 15 -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0, sst39lf/vf100 device id = 2788h, is read with a 0 = 1 5555h aah 2aaah 55h 5555h 90h software id exit 7 7. both software id exit operations are equivalent xxh f0h software id exit 7 5555h aah 2aaah 55h 5555h f0h t4.5 363
6 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange : sst39lf100 range ambient temp v dd commercial 0c to +70c 3.0-3.6v o perating r ange : sst39vf100 range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf for sst39lf100 output load . . . . . . . . . . . . . . . . . . . . . c l = 100 pf for sst39vf100 see figures 11 and 12
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 7 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 table 5: dc o perating c haracteristics v dd = 3.0-3.6v for sst39lf100 and 2.7-3.6v for sst39vf100 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht , at f=1/t rc min, v dd =v dd max read 30 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 30 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 20 a ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v dd =v dd min v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =3 ma, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t5.7 363 1. typical conditions for the active current shown on the front data sheet page are average values at 25c (room temperature), and v dd = 3v for vf devices. not 100% tested. table 6: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t6.0 363 table 7: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t7.0 363 table 8: r eliability c haracteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycle minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t8.2 363
8 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 ac characteristics table 9: r ead c ycle t iming p arameters v dd = 3.0-3.6v for sst39lf100 and 2.7-3.6v for sst39vf100 symbol parameter sst39lf100-45 sst39vf100-70 units minmaxminmax t rc read cycle time 45 70 ns t ce chip enable access time 45 70 ns t aa address access time 45 70 ns t oe output enable access time 20 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 15 20 ns t ohz 1 oe# high to high-z output 15 20 ns t oh 1 output hold from address change 0 0 ns t9.4 363 table 10: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms t10.1 363
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 9 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 2: r ead c ycle t iming d iagram figure 3: we# c ontrolled p rogram c ycle t iming d iagram 363 ill f03.1 address a 15-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 363 ill f04.2 address a 15-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: x can be v il or v ih , but no other value
10 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 4: ce# c ontrolled p rogram c ycle t iming d iagram figure 5: d ata # p olling t iming d iagram 363 ill f05.2 address a 15-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: x can be v il or v ih , but no other value 363 ill f06.1 address a 15-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 11 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 6: t oggle b it t iming d iagram figure 7: we# c ontrolled c hip -e rase t iming d iagram 363 ill f07.1 address a 15-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs 363 ill f08.5 address a 15-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 10) x can be v il or v ih , but no other value.
12 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 8: we# c ontrolled s ector -e rase t iming d iagram figure 9: s oftware id e ntry and r ead 363 ill f18.4 address a 15-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 10) sa x = sector address x can be v il or v ih , but no other value. 363 ill f09.4 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bfh device id xx55 xxaa xx90 device id = 2788h for sst39lf/vf100 x can be v il or v ih , but no other value.
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 13 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 10: s oftware id e xit 363 ill f10.1 address a 14-0 x can be v il or v ih , but no other value. t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 dq 15-0
14 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 11: ac i nput /o utput r eference w aveforms figure 12: a t est l oad e xample 363 ill f11.1 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 363 ill f12.2 to tester to dut c l 1.3 v 1n914 3.3 k ?
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 15 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 13: w ord -p rogram a lgorithm 363 ill f13.3 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed x can be v il or v ih but no other value.
16 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 14: w ait o ptions 363 ill f14.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 17 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 15: s oftware p roduct id c ommand f lowcharts 363 ill f15.2 load data: xxaah address: 5555h software id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h software id exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih , but no other value.
18 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 figure 16: e rase c ommand s equence 363 ill f16.3 load data: xxaa address: 5555 chip-erase command sequence load data: xx55 address: 2aaa load data: xx80 address: 5555 load data: xx55 address: 2aaa load data: xx10 address: 5555 load data: xxaa address: 5555 wait t sce chip erased to ffffh load data: xxaa address: 5555 sector-erase command sequence load data: xx55 address: 2aaa load data: xx80 address: 5555 load data: xx55 address: 2aaa load data: xx30 address: sa x load data: xxaa address: 5555 wait t se sector erased to ffffh x can be v il or v ih , but no other value.
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 19 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 product ordering information valid combinations for sst39lf100 sst39lf100-45-4c-wi sst39lf100-45-4c-b3k sst39lf100-45-4c-wie sst39lf100-45-4c-b3ke valid combinations for sst39vf100 sst39vf100-70-4c-wi sst39vf100-70-4c-b3k sst39vf100-70-4c-wie sst39vf100-70-4c-b3ke SST39VF100-70-4I-WI sst39vf100-70-4i-b3k SST39VF100-70-4I-WIe sst39vf100-70-4i-b3ke note: valid combinations are those products in mass production or will be in mass production. consult your sst sales rep- resentative to confirm availability of valid combinations and to determine availability of new combinations. environmental attribute e = non-pb package modifier i = 40 leads k = 48 balls package type b3 = tfbga (0.8mm pitch, 6mm x 8mm) w = tsop (type 1, die up, 10mm x 14mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 45 = 45 ns 70 = 70 ns device density 100 = 1 mbit voltag e l = 3.0-3.6v v = 2.7-3.6v product series 39 = multi-purpose flash sst 39 vf 100 - 70 - 4c - b3k e xx x x xxxx - xxx -xx -xxx x
20 data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 packaging diagrams 40- lead t hin s mall o utline p ackage (tsop) 10 mm x 14 mm sst p ackage c ode : wi 12.50 12.30 14.20 13.80 0.70 0.50 10.10 9.90 0.27 0.17 1.05 0.95 0.15 0.05 0.70 0.50 40-tsop-wi-7 note: 1. complies with jedec publication 95 mo-142 ca dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. pin # 1 identifier 0. 50 bsc 1.20 max. 1mm 0?- 5? detail
data sheet 1 mbit multi-purpose flash sst39lf100 / sst39vf100 21 ?2003 silicon storage technology, inc. s71129-04-000 11/03 363 48- ball t hin - profile , f ine - pitch b all g rid a rray (tfbga) 6 mm x 8 mm sst p ackage c ode : b3k table 11: r evision h istory number description date 02 2002 data book may 2002 03 changes to table 5 on page 7 ? added footnote for typical conditions ? clarified the test conditions for power supply current and read parameters added footnote for non-pb packages mar 2003 04 2004 data book added non-pb mpns and removed footnote. (see page 19) updated mechanical diagram for b3k package. nov 2003 a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

▲Up To Search▲

Price & Availability of SST39VF100-70-4I-WI

	To Download SST39VF100-70-4I-WI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .